Simplified Current-Steering DAC Design for Lower Power and Increased Settling Time Using Half Rate Clocking

February 3, 2012
633 Mudd
Hosted by: Columbia Integrated Systems Lab
Dr. Bob Schell (Analog Devices, Inc.)


Digital to analog converters have found their way into a variety of applications from static control loops, offset adjustments, baseband signal synthesis and increasingly for direct RF signal synthesis. As the output signal frequency increases, the DAC aspect that limits spectral performance (distortion) changes, bringing up new design goals. This talk starts by discussing DAC designs for DC to low frequency output signals and moves on to discuss design goals for high output frequencies. In this vein I present a new technique targeted at alleviating incomplete settling issues for high speed DACs, utilizing half rate clocking of a quad switch. By halving the frequency, the settling time allowed for clocks at the switches (as well as signals within the whole datapath) is doubled, reducing data dependencies for improved performance.

Speaker Biography

Bob Schell received his BSE from Princeton University and his MS and PhD degrees from Columbia University. He has worked as a product engineer for MultiLink Technologies and Vitesse Semiconductor and as a design engineer for Conexant. He is currently a senior mixed signal designer working for Analog Devices in NJ. His interests are in both analog-to-digital and digital-to-analog converter design as well as serial high speed serial interfaces required by both of these blocks.

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