Power-aware High-data-rate Communication Circuits

April 10, 2008
Time: 11:00am-12:00pm
Interschool Lab, Room 750 CEPSR
Speaker: Sudip Shekhar, University of Washington


Appliances based on communication systems have become an integral part of our lives, and their influence is bound to increase in the future for diverse domains like multi-core computing, mobile connectivity, automobile guidance, personal healthcare, gaming and entertainment, etc. Relentless advances in CMOS technology allow these systems to attain very high date rates. Performance per watt is a key design metric, along with cost and area. Innovations at the architecture and circuit levels are required; specific examples of wireline and wireless transceivers are presented in this talk.

To enable future multi-core microprocessors with large aggregate bandwidths, high data-rate parallel links must be realized with low-power. Successfully recovering the high-speed data in the presence of inter-symbol interference depends crucially on low clock jitter and precise clock phase deskewing. A method of both filtering and deskewing a link clock using an injection-locked LC-VCO (voltage-controlled oscillator) is described, and the first forwarded-clock data receiver operating at 27Gb/s is presented.

Wireless standards like UMTS, Bluetooth, WLAN, Edge, etc., continue to evolve in the pursuit of higher data rates. This plethora of options demands a re-configurable transmitter that automatically adapts to the best local standard at an optimized power and performance level. The polar transmitter topology is, in many ways, an attractive candidate for achieving a reconfigurable solution. However, efficient wideband modulation schemes need to be incorporated in it. Towards this goal, circuits and systems innovations in a fractional frequency synthesizer are presented that promise a wide-band phase modulator for a Bluetooth enhanced data rate transmitter.

Speaker Biography

Sudip Shekhar received the B. Tech. degree (Honors) in Electronics and Electrical Communication Engineering from the Indian Institute of Technology, Kharagpur, in 2003. He received the M.S. degree in Electrical Engineering from the University of Washington, Seattle, in 2005, where he is currently working toward the Ph.D. degree. In the summers of 2005, 2006, and 2007, he was a Ph.D. intern with the Intel Corporation, Hillsboro, OR.

Mr. Shekhar is a recipient of a 2007-2008 IEEE Solid-State Circuits Society Pre-doctoral Fellowship, a 2006–2008 Intel Foundation Ph.D. Fellowship, and the 2007 Analog Devices Outstanding Student Designer Award.

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