Manycore Vector-Thread Architectures

March 12, 2009
Interschool Lab, Room 750 CEPSR
Speaker: Christopher F. Batten, , Ph.D. Candidate, Computer Science and Artificial Intelligence Lab at MIT


Serious technology issues are breaking down the traditional abstractions in computer engineering. Power and energy consumption are now first-order design constraints and the road map for standard CMOS technology has never been more challenging. In response to these technology issues, computer architects are turning to multicore and manycore processors where tens to hundreds of cores are integrated on a single chip. However, this breaks down the traditional sequential execution abstraction forcing software programmers to parallelize their applications. This talk will introduce a new architectural approach called vector-threading (VT) which is a first step to addressing these challenges. Vector-threading combines the energy-efficiency and simple programming model of vector execution with the flexibility of multithreaded execution.

This talk will also describe two implementations of vector-threading. The Scale VT Processor is a prototype for embedded applications implemented in a TSMC 0.18um process. Scale includes a RISC control processor and a four-lane vector-thread unit that can execute 16 operations per cycle and supports up to 128 active threads. The 16 mm^2 chip runs at 260 MHz while consuming 0.4-1.1 W across a range of kernels. We have leveraged our insights from our first implementation of vector-threading to begin developing the Maven VT Processor. A Maven chip would include tens to hundreds of simple control processors each with its own single-lane vector-thread unit (VTU). A Maven single-lane VTU is potentially easier to implement and more efficient than a Scale multiple-lane VTU. Maven lanes can be coupled together with a combination of low-level software running on the control processor and fast hardware barriers.


Christopher Batten is a Ph.D. candidate in the Electrical Engineering and Computer Science Department at the Massachusetts Institute of Technology. He is currently finishing his thesis research as a visiting student at the University of California, Berkeley in the new Parallel Computing Laboratory. He holds a B.S. in Electrical Engineering from the University of Virginia and an M.Phil. in Engineering from the University of Cambridge, UK where he studied as a Winston Churchill Scholar. His research interests include energy-efficient parallel computer architecture and leveraging emerging technologies such as silicon photonics to benefit future parallel applications.

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