Design for Robustness in Extreme Scaling and 3D-IC

March 12, 2013
EE Conference Room
Hosted by: Prof. Ken Shepard
Speaker: Dr. David Z. Pan (University of Texas at Austin, Dept. of Electrical and Computer Engineering)


As the CMOS feature enters the era of extreme scaling (14nm, 11nm and beyond), the printability challenges are exacerbated. Meanwhile, the vertical scaling with 3D-IC integration using through-silicon- vias (TSVs) has gained tremendous momentum and initial industry adoption, which can further extend the Moore’s Law even the horizontal scaling stops ultimately. However, as TSV involves disruptive manufacturing technologies, new modeling and design techniques need to be developed for robust 3D IC integration. In this talk, I will first present some of our recent results to push the nanolithography limit with novel design techniques, for multiple patterning lithography as well as other emerging lithography technologies. In 3D-IC, TSVs may cause significant thermal mechanical stress, which not only results in systematic mobility and performance variations, but also leads to mechanical and electrical reliability concerns. I’ll discuss full-chip/package modeling and physical design for reliable 3D-IC integration.

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