Continuous-Time Delta Sigma Data Converters with Reduced Clock Jitter Sensitivity and Enhanced Linearity

April 12, 2013
Interschool Lab (750 CEPSR)
Speaker: Prof. Shanthi Pavan (IIT Madras)


Clock jitter degrades the performance of a continuous-time delta sigma converter. A common approach to addressing this issue is the use of a switched capacitor feedback DAC. Unfortunately, using such a DAC can severely degrade the modulator's linearity. In this talk, I will describe the Switched-Capacitor Return-to-Zero DAC, which is a recent technique that improves jitter immunity and modulator linearity at the same time. A modulator test chip designed and fabricated in a 0.18um CMOS process achieves 87dB dynamic range in a 2MHz bandwidth.

Speaker Biography

Shanthi Pavan obtained the B.Tech degree in Electronics and Communication Eng. from the Indian Institute of Technology, Madras in 1995 and the M.S and Sc.D degrees from Columbia University, New York in 1997 and 1999 respectively. After working in industry for a few years, he moved to the Indian Institute of Technology-Madras, where he is now a Professor of Electrical Engineering. His research interests are in the areas of high speed analog circuit design, sensing and signal processing.

Prof. Pavan is the recipient of the 2012 Shanti Swarup Bhatnagar Award in Engineering Sciences from the Government. of India, the IEEE Circuits and Systems Society Darlington Best Paper Award (2009), the Swarnajayanthi Fellowship (2010, from the Government of India) , the Young Faculty Recognition Award from IIT Madras (2009, for excellence in teaching) , the Technomentor Award from the India Semiconductor Association (2010) and the Young Engineer Award from the Indian National Academy of Engineering (2006). He is the Deputy Editor in Chief of the IEEE Transactions on Circuits and Systems: Part I - Regular Papers and serves on the Data Converter Committee of the International Solid State Circuits Conference (ISSCC).

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