A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500MHz-to-8 GHz) All Digital CMOS ADPLL in 65nm SOI

February 23, 2007
Time: 2:00pm-3:00pm
EE Conference Room 1312 S.W. Mudd
Hosted by: Columbia Integrated System Laboratory
Speaker: Dr. Tierno, IBM T.J. Watson Research Center

Abstract

An all static CMOS ADPLL fabricated in 65 nm digital CMOS SOI technology has a fully programmable PDI loop filter and features a third order delta sigma modulator. The DCO is a three stage, static inverter based ring oscillator programmable in 768 frequency steps. The ADPLL locks from 500 MHz to 8 GHz at 1.3V and 25°C, and from 90 MHz to 1.2 GHz at 0.5V and 100°C. The IC dissipates 8 mW/GHz at 1.2V and 1.6 mW/GHz at 0.5V. The synthesized 4 GHz clock has a period jitter of 0.7 ps rms, and long term jitter of 6 ps rms. The phase noise is -112 dBc/Hz at 4 GHz center frequency 10 MHz offset. The total circuit area is 200 um x 150 um.


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