April 2, 2010
Speaker: Dr. Poras Balsara, University of Texas, Dallas
As CMOS technology shrink and device densities on a chip increase, power dissipationis rapidly becoming the most important design concern. This talk will present some early results from our recent work involving device sizing for low power digital design. The technique presented will enable quick exploration of different architectures and circuit topologies in order to analyze energy and delay trade-offs for a given functional block in a system.
Poras T. Balsara is a Professor of Electrical Engineering at the University of Texas at Dallas. He received his MS and PhD degree from the Penn State University in 1985 and 1989, respectively. His research interests include, VLSI design, design of energy efficient digital systems, circuits and systems for DSP and communications, digitally-intensive RF and mixed-signal circuits, and computer arithmetic. He has published several journal and conference papers in these areas